Optimizing Energy Efficiency in Modern
Computing Systems through Advanced
Architectural Techniques
by Yu-Yang Ting and Wei Chen
Introducon
In the contemporary era of rapid technological advancement, opmizing energy
eciency in modern compung systems has emerged as a crical challenge and an area
of intensive research. The push towards more sustainable and energy-ecient
compung pracces is driven by the exponenal growth in data processing needs, the
proliferaon of cloud compung, and the ubiquitous deployment of internet-connected
devices. The quest for minimizing energy consumpon while maximizing performance
has led to the exploraon of advanced architectural techniques that promise signicant
improvements in energy eciency. This literature review aims to dissect the myriad of
strategies and innovaons in computer architecture that contribute to energy
conservaon, ranging from novel processing units and memory management techniques
to predicve models and energy-aware algorithms. By synthesizing ndings from cung-
edge research, including studies on Non-Uniform Memory Access (NUMA) opmizaons,
Simultaneous Multhreading (SMT) enhancements, dynamic voltage and frequency
scaling (DVFS), and the implementaon of machine learning algorithms for energy
predicon, this review provides a comprehensive overview of the state-of-the-art
approaches to energy-ecient compung. Through the lens of recent advancements
and empirical studies, we aim to highlight the eecveness of these architectural
innovaons, idenfy prevailing challenges, and propose future direcons for research in
opmizing energy eciency in modern compung systems.
Methodology
Our methodology for the literature review on opmizing energy eciency in modern
compung systems encompasses a systemac search across academic databases,
applying inclusion and exclusion criteria to select relevant studies, extracng and
assessing data from these studies, synthesizing ndings to idenfy trends and gaps, and
analyzing the impact of architectural techniques on energy eciency. This approach
ensures a comprehensive and crical examinaon of current research in the eld.
Result
In this secon, we delve into the mulfaceted strategies and innovaons that have been
explored to enhance energy eciency in modern compung systems through advanced
architectural techniques. Our discussion encompasses a range of approaches from
hardware opmizaons, such as Non-Uniform Memory Access (NUMA) adjustments and
Simultaneous Multhreading (SMT) enhancements, to soware intervenons like
dynamic voltage and frequency scaling (DVFS) and predicve modeling. Each strategy is
examined for its potenal to reduce energy consumpon while maintaining or improving
performance, illustrang the complexity and necessity of cross-disciplinary eorts in
achieving sustainable compung pracces.
NUMA opmizaon
The arcle "Energy-ecient I/O Thread Schedulers for NVMe SSDs on NUMA" [1]
presents a thorough invesgaon into the performance and energy eciency of using a
large number of parallel I/O threads. This study highlights that when managing I/O
operaons on Non-Uniform Memory Access (NUMA) architectures with NVMe Solid
State Drives (SSDs), the impact of CPU contenon—where mulple processes compete
for CPU me—is signicantly less detrimental than the impact of remote access. Remote
access refers to the process of accessing data from SSDs that are not directly connected
to the CPU aempng the access, which is a common scenario in NUMA systems. These
ndings suggest that opmizing for reduced remote access to NVMe SSDs could lead to
more substanal performance and energy eciency improvements than merely focusing
on minimizing CPU contenon in systems employing numerous parallel I/O threads.
So, they present a new algorithm on NVMe SSDs on NUMA - ENERGY-EFFICIENT I/O
SCHEDULER(ESN)
Background-NUMA
In the class, we have learned about Symmetric Mulprocessing (SMP). SMP involves a
system where all CPUs share the same memory resources via the same memory bus,
ensuring equal access speeds for all processors, hence the term "symmetric." However,
as the number of CPUs increases, memory access conicts also rise, leading to a rapid
decline in the eciency and performance of the CPUs. On the other hand, Non-Uniform
Memory Access (NUMA) divides CPUs into mulple nodes, with each node possessing its
own independent memory space, allowing for high-speed interconnect communicaon
between nodes. In NUMA architectures, the speed at which a CPU accesses memory
varies depending on the node; accessing local node memory is fastest, while accessing
remote node memory is slower, with speed decreasing as the distance increases. This
design inherently suers from slower access speeds when a node's memory is
insucient and data must be retrieved from a remote node.
Figure 1 SMP vs NUMA
NVMe SSDs on NUMA
Figure 2 NVMe SSDs on NUMA
In the nuanced landscape of NUMA (Non-Uniform Memory Access) architectures, the
placement of NVMe (Non-Volale Memory express) Solid-State Drives (SSDs) becomes
pivotal to system performance. Referencing the visual aids provided in the gures, we
explore three sengs: The rst shows a single SSD coupled to one CPU node (gure 3),
potenally decreasing latency and memory contenon through direct local access. The
second seng involves a dual-SSD setup, each connected to individual CPU nodes
(gure 5), harnessing parallelism and diminishing memory trac across nodes, which is
benecial for high-throughput demands. The third seng depicts two SSDs connected to
a single CPU node (gure 4), which might enhance storage bandwidth at the cost of
increasing contenon for memory access. As the gures suggest, remote memory
access, a fundamental aspect of NUMA systems, oen entails augmented latency and
access disputes. Consequently, the strategic arrangement of SSDs relave to CPU nodes
is a crical consideraon, with the goal of reducing the detriments of remote access,
thereby underlining the importance of tailored SSD sengs to enhance the eciency
and speed of the overall system.
Figure 3 Single SSD NUMA seng [1]
Figure 4 Dual SSDs NUMA seng 1 [1]
Figure 5 Dual SSDs NUMA seng 2 [1]
Expanding upon the insights presented in Figure 6, it becomes apparent that system
throughput experiences a decline when the number of I/O threads surpasses the
threshold of 512 in Seng 1 of Conguraon 1. This specic seng involves a solitary
SSD bound to a single CPU node. The degradaon in performance at this juncture can be
primarily aributed to a heightened contenon penalty, which, in this scenario, imposes
a more substanal boleneck than the penalty incurred through remote access. The
contenon penalty arises as mulple I/O threads vie for access to the limited resources
of the single SSD, resulng in an increased number of conicts and, consequently,
latency. This outcome underlines the intricate balance between resource allocaon and
scalability within NUMA architectures. It emphasizes the need for meculous planning in
the architectural design phase to accommodate the ancipated load and access
paerns, thereby ensuring that the system is not only well-tuned for current demands
but also scalable for future increases in load without signicant performance trade-os.
Figure 6 single SSD on NUMA benchmark
Turning our aenon to the dual-SSD NUMA conguraons across dierent sengs, a
disnct divergence in performance becomes evident. As illustrated in the data, Seng 1
achieves a superior maximum throughput, approximately 1600 IOPS, whereas Seng 2
peaks at merely 1200 IOPS. The crical factor contribung to this discrepancy is the
unique conguraon of Seng 2, where both SSDs are aliated with a singular CPU
node. Although this node has the advantage of localized access to the data stored within
the SSDs, it is simultaneously hampered by the dual penales of contenon and remote
access. Contenon arises as the two SSDs on the same node compete for bandwidth,
while other nodes incur a performance hit when aempng to access these SSDs
remotely, leading to a compounded delay. In contrast, Seng 1, by distribung the SSDs
across two CPU nodes, alleviates such contenon and minimizes remote access
requirements, thus facilitang a higher throughput. This comparison underscores the
necessity of considering both the placement of storage resources and the intended
access paerns to opmize NUMA system performance comprehensively.
Figure 7 Seng 2 benchmark [1]
Figure 8 seng 1 benchmark [1]
Linux default scheduler-CFS
In the referenced arcle [1], the "default scheduler" denotes the Linux kernel's default
I/O scheduler, known as the Completely Fair Scheduler (CFS). The CFS is designed to
allocate me slices for process execuon in a manner that aims to provide equitable CPU
me to running processes, thereby ensuring a balanced distribuon of compung
resources. This arcle delves into the performance metrics of I/O operaons within
systems employing a single NVMe SSD and notes that prior assessments of I/O
performance have predominantly been under condions where the CFS is operaonal.
CFS plays a pivotal role in managing how tasks are priorized and executed, extending its
inuence to the I/O performance by managing access to the storage subsystem. In the
context of NUMA systems, where mulple processors are involved, CFS must also
account for the addional complexity introduced by remote accesses—where data must
be fetched across dierent memory nodes. The scheduler thus faces the dual challenge
of managing equitable CPU access (its primary funcon) while also navigang the
penales associated with remote storage access. These penales can exacerbate the
latency issues, especially when numerous I/O threads concurrently request access to
storage resources that are not locally available.
Therefore, the scheduler's behavior can signicantly impact system performance,
parcularly in NUMA conguraons. Understanding and potenally opmizing the
default scheduler's strategy for handling I/O requests is crucial for enhancing overall
system eciency, parcularly in sengs with high I/O demands and in systems that are
sensive to latency variaons due to remote access penales.
Energy-ecient I/O scheduler (ESN)
Figure 9 ESN algorithm
The ESN (Energy-ecient Scheduler for NUMA systems) algorithm presents a set of
enhancements tailored for the unique demands of NUMA architectures. It focuses on
distribung loads equitably across nodes to avert bolenecks, thereby opmizing
resource ulizaon. By priorizing local memory access, ESN reduces the latency
typically associated with remote accesses, leading to speedier data retrieval and
diminishing energy expenditure. The algorithm also curtails resource contenon, which
is essenal for maintaining consistent performance levels, especially under the strain of
mulple concurrent processes.
Furthermore, ESN showcases impressive scalability. It adapts to the demands of
escalang parallel processes without the necessity for manual intervenon, a crical
feature for dynamic high-performance compung environments. In terms of energy
conservaon, ESN strategically aligns I/O threads with CPU sockets, taking into account
both the number of processes and the locaon of memory accesses. This alignment
ensures opmal system performance while concurrently reducing power consumpon
by perming the idling of CPUs not engaged in acve tasks. The core objecve of ESN is
thus to intelligently map an increased number of I/O threads to the same CPU, while
judiciously balancing performance consideraons. The culminaon of these mapped
threads allows for the potenal downscaling of energy usage by placing unused CPUs in
a low-power state, thereby enhancing the overall energy eciency of the system.
Improvement
Figures 10 through 13 provide a comparave performance analysis between the ESN
scheduler and the tradional CFS scheduler for systems ulizing a single NVMe SSD.
These gures highlight that the ESN scheduler not only preserves a similar level of
throughput to that of the CFS but also excels in diminishing latency. Moreover, ESN
demonstrates a notable reducon in energy consumpon, an advantage achieved by its
ability to idle CPUs when they are not in acve use. This capability of ESN to maintain
operaonal eciency while enhancing power management underscores its suitability for
energy-conscious compung environments.
Figure 10 CFS vs ESN [1]
Figure 11 CFS vs ESN [1]
Figure 12 CFS vs ESN [1]
Figure 13 CFS vs ESN [1]
Discussion & Conclusion
References
[1]
H. J. W. S.-a. a. S. S. J. Qian, Energy-ecient I/O Thread Schedulers for NVMe SSDs
on NUMA, 2017 17th IEEE/ACM Internaonal Symposium on Cluster, Cloud and Grid
Compung, 2017.
